The present invention relates to an apparatus and a method for providing round-robin arbitration between requests for access to a shared resource such as a data bus, shared by a plurality of hardware modules, as mentioned in the preamble of claims 1 and 11, respectively.
Arbitration systems of this kind are normally configured in a so-called master-slave configuration, in which a module seeking access to the shared resource sends a request to the master module and the master module controls the arbitration by polling, sending grant signals to the requesting modules in a round-robin scheme. Communication is only possible between the master and a slave, not between slaves.
From U.S. Pat. No. 5,072,363 a system providing round-robin arbitration between requests for access to a shared resource such as a data bus, shared by a plurality of hardware modules is known, said system comprising a central counter cyclically driven between multiple count states by a clock, each count state being associated with a request for access to the shared resource by one of the plurality of hardware modules. In this system, the arbiter receives each individual request for access to the shared resource on separate request lines connected between the arbiter and the modules. Correspondingly, the arbiter grants access to the shared resource via separate grant lines connected between the arbiter and the modules. This involves at least two lines between the arbiter and each of the hardware modules. Furthermore, the arbitration is performed using a programmable array logic and a bus arbitration module and programming of the programmable array logic and the setup of input/output lines have to be individually adapted in accordance with the number of modules involved in each individual case, thereby reducing the flexibility of the system.
EP-0,286,235 describes arbitration in which the bus controller issues a xe2x80x9csendxe2x80x9d command and an xe2x80x9caddressxe2x80x9d on the bus to be shared by the processors and the addressed processor responds by using the bus or by sending a NACK-signal on the bus. The processor has only access to the bus for a predetermined limited time period. Thus, this arbitration system is totally unsuited for controlling the access to e.g. a serial HDLC-bus, in which the time needed for sending an HDLC-frame can be considered stochastic.
It is the object of the present invention to provide an apparatus and a method of the above kind, which is of simple construction. This object is achieved with an apparatus as stated in claim 1 and a method as stated In claim 11. Hereby it is achieved that the arbitration can be implemented using a simple construction, including a simple counter, simple comparators and simple gates. Preferred embodiments of the invention are revealed in the sub-ordinate claims.